Description of the Conventional Art
Electrostatic discharge (ESD) occurs when the static electricity caused by electric field induction and/or friction between objects is discharged through a semiconductor chip. As conventional semiconductor chips become increasingly integrated, static electricity may be introduced into wires through pads and may damage the semiconductor chips. To protect circuits inside or on semiconductor chips from ESD, conventional semiconductor chips may include an ESD protection circuit.
An ESD protection circuit may be arranged near the pads of the semiconductor chip, and/or between the pad and the main circuit of the chip. When static electricity is introduced through the pads, the ESD protection circuit protects circuits inside or on (e.g., the main circuit) of the semiconductor chip against the static electricity by discharging the static electricity through a designated path.
FIG. 1 is a schematic view showing a conventional arrangement of pads on a conventional semiconductor chip. As shown, a plurality of pads may be formed in a staggered structure on one side of a semiconductor chip 1. Data and/or control signals may be transmitted and received to and from the external circuit. As conventional semiconductor chips become increasingly integrated, the number of channels arranged on the semiconductor chip may increase. However, as the size of the semiconductor chip is reduced, the size of each pad arranged on the chip and/or the area on which the pads are placed may decrease.
Referring still to FIG. 1, the plurality of pads may be arranged on the semiconductor chip 1 in one or more rows. The plurality of pads shown in FIG. 1 may be arranged in a first row 2a on an outer side of the semiconductor chip and a second row 2b on an inner side of the semiconductor chip. The first row of pads 2a and the second row of pads 2b may be arranged in a zigzag or staggered arrangement, such that each pad in the second row of pads 2b falls between two pads in the first row of pads 2a. 
FIG. 2 is a circuit diagram showing an example operation of a conventional ESD protection circuit. As shown, the conventional ESD protection circuit may include an internal circuit 3 for transmitting and receiving signals to and from an external circuit through the pad. The internal circuit 3 may be connected to the pad through a resistor R.
The ESD protection circuit of FIG. 2 may include one or more diodes. For example, the ESD protection circuit may include a first diode D1 and a second diode D2. The first diode D1 and the second diode D2 may be connected between the pad and a power clamp 4, and may transmit currents i1 and i2. The currents i1 and i2 may be induced by static electricity introduced through the pad to the power clamp 4.
Conventionally, the extent to which the size of a semiconductor chip may be reduced may be limited by the ESD protection circuit. For example, the size of the semiconductor chip may be determined based on the size of the ESD protection circuit.
FIG. 3 is a block diagram showing a conventional ESD protection circuit having a pad on I/O (POI) structure. FIG. 3 shows two outer pads 21 and 22 from first row 2a of FIG. 1, and an inner pad 23 from second row 2b of FIG. 1. Each of the pads 21, 22 and 23 may be connected to an ESD protection circuit for protecting an internal circuit of the semiconductor chip. For example, outer pads 21 and 22 may be connected to ESD protection circuits 31 and 32, respectively, and inner pad 23 may be connected to an ESD protection circuit 33. Each of the ESD protection circuits 31, 32 and 33 may include an N-type diode and a P-type diode.
An N-type diode 31a and a P-type diode 31b may be arranged under and connected to the outer pad 21. An N-type diode 32a and a P-type diode 32b may be arranged under and connected to the outer pad 22. An N-type diode 33a and a P-type diode 33b may be arranged under and connected to the inner pad 23.
A conventional semiconductor chip having the structure of FIG. 3 may have more stable ESD characteristics; however, ESD protection circuits arranged under outer pads and inner pads may increase the vertical size of the chip.
For example, each pad may have a horizontal width and the vertical length. As the number of the pads increases, the width of the pad may decrease. However, even if the ESD arranged under the inner pad is moved to the outer empty area of the chip, the size of ESD protection circuits required for higher voltage processes may increase, which may limit the maximum number of the pads.